职位描述
Job Title: Senior IP Design Verification Engineer Location: Beijing/Shanghai Position Description Candidate will be one member of IP Verification team to finish the verification tasks of specific IP in time and in high quality. Responsibilities Create the testplan and review with the team leader and designer Create the random constraint testbench per requirements Create the random/direct testcases to cover IP design features Debug the testbench and RTL Finish the verification tasks in time Qualifications Education and Experience Bachelor or above with 3 years of work experience Skills and Knowledge Verilog System Verilog UVM Perl/Python/Tcl C++ is an additional plus Formal verification experience is an additional plus PCIE/SATA/USB/Ethernet/SPI/I2C/etc. experience is an additional plus ARM related experience is an additional plus 职能类别： IC验证工程师 关键字： verification uvm arm IP 验证 微信分享
